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CY2412
MPEG Clock Generator with VCXO
Features
* Integrated phase-locked loop (PLL) * Low-jitter, high-accuracy outputs * VCXO with analog adjust * 3.3V operation * 8-pin SOIC package
Benefits
* Highest-performance PLL tailored for multimedia applications * Meets critical timing requirements in complex system designs * Large 150-ppm range, better linearity * Enables application compatibility
Part Number CY2412-1 CY2412-3
Outputs 3 3
Input Frequency Range 13.5-MHz pullable crystal input per Cypress specification 13.5-MHz pullable crystal input per Cypress specification
Output Frequencies
VCXO Profile
Two 27 MHz outputs, one 54 MHz (3.3V) Linear 27 MHz, 13.5 MHz, 54 MHz (3.3V) Linear
Logic Block Diagram
Pin Configuration
CY2412-1,-3 8-pin SOIC
XIN VDD VCXO VSS 1 2 3 4 8 7 6 5 XOUT CLKC CLKB CLKA
CLKC 13.5 XIN XOUT OSC Q
P
VCO
OUTPUT DIVIDERS
CLKB
CLKA
VCXO
PLL
VDD
VSS
Cypress Semiconductor Corporation Document #: 38-07227 Rev. *D
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised December 13, 2004
CY2412
Pin Summary
Pin Name XIN VDD VCXO VSS CLKA CLKB CLKC XOUT[2] 1 2 3 4 5 6 7 8 Pin Number Reference Crystal Input Voltage Supply Input Analog Control for VCXO Ground 54-MHz clock output 13.5-MHz clock output 27-MHz clock output Reference Crystal Output Pin Description
Pullable Crystal Specifications[1]
Parameter FNOM CLNOM R1 R3/R1 DL F3SEPHI F3SEPLO C0 C0/C1 C1 Description Nominal crystal frequency Nominal load capacitance Equivalent series resistance (ESR) Fundamental mode Ratio of third overtone mode ESR to funda- Ratio used because typical R1 mental mode ESR values are much less than the maximum spec. Crystal drive level Third overtone separation from 3*FNOM Third overtone separation from 3*FNOM Crystal shunt capacitance Ratio of shunt to motional capacitance Crystal motional capacitance No external series resistor assumed High side Low side Condition Parallel resonance, fundamental mode, AT cut Min. - - - 3 Typ. 13.5 14 - - Max. Unit - - 25 - MHz pF
- 300 - - 180 14.4
0.5 - - - - 18
2.0 - 7 250 21.6
mW ppm pF pF
-150 ppm
Note: 1. Crystals that meet this specification includes: Ecliptek ECX-5788-13.500M,Siward XTL001050A-13.5-14-400, Raltron A-13.500-14-CL,PDI HA13500XFSA14XC.
Document #: 38-07227 Rev. *D
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CY2412
Absolute Maximum Conditions
Parameter VDD TS TJ Description Supply Voltage Storage Temperature[3] Junction Temperature Digital Inputs Digital Outputs referred to VDD Electrostatic Discharge Min. -0.5 -65 - VSS - 0.3 VSS - 0.3 2 Max. 7.0 125 125 VDD + 0.3 VDD + 0.3 Unit V C C V V kV
Recommended Operating Conditions
Parameter VDD TA CLOAD fREF tPU Description Operating Voltage Ambient Temperature Max. Load Capacitance Reference Frequency Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) 0.05 13.5 500 Min. 3.14 0 Typ. 3.3 Max. 3.47 70 15 Unit V C pF MHz ms
DC Electrical Characteristics
Parameter IOH IOL CIN IIZ fXO VVCXO fVBW IDD Description Output High Current Output Low Current Input Capacitance Input Leakage Current VCXO pullability range VCXO input range VCXO input bandwidth Supply Current Sum of Core and Output Current +150 0 DC to 200 35 VDD 5 Test Conditions VOH = VDD - 0.5, VDD = 3.3V VOL = 0.5, VDD = 3.3V Min. 12 12 Typ. 24 24 7 Max. Unit mA mA pF A ppm V kHz mA
AC Electrical Characteristics
Parameter[4] DC ER EF t9 t10 Description Output Duty Cycle Rising Edge Rate Falling Edge Rate Clock Jitter PLL Lock Time Test Conditions Duty Cycle is defined in Figure 1, 50% of VDD Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF. See Figure 2. Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF. See Figure 2. Peak to Peak period jitter Min. 45 0.8 0.8 Typ. 50 1.4 1.4 100 200 3 Max. 55 Unit % V/ns V/ns ps ms
Notes: 2. Float XOUT if XIN is externally driven. 3. Rated for ten years. 4. Not 100% tested.
Document #: 38-07227 Rev. *D
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CY2412
t1 t2
CLK
50%
50%
Figure 1. Duty Cycle Definition; DC = t2/t1
t3 80%
t4
CLK
20%
Figure 2. Rise and Fall Time Definitions: ER = 0.6 x VDD / t3 , EF = 0.6 x VDD / t4
Test Circuit VDD 0.1 F OUTPUTS CLK out CLOAD
GND Ordering Information
Ordering Code CY2412SC-1 CY2412SC-1T CY2412SC-3 CY2412SC-3T Lead-free CY2412SXC-1 CY2412SXC-1T CY2412SXC-3 CY2412SXC-3T 8-pin SOIC 8-pin SOIC-Tape and Reel 8-pin SOIC 8-pin SOIC-Tape and Reel Commercial Commercial Commercial Commercial 3.3V 3.3V 3.3V 3.3V 8-pin SOIC 8-pin SOIC-Tape and Reel 8-pin SOIC 8-pin SOIC-Tape and Reel Package Type Operating Range Commercial Commercial Commercial Commercial Operating Voltage 3.3V 3.3V 3.3V 3.3V
Document #: 38-07227 Rev. *D
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CY2412
Package Diagram
8 Lead (150 Mil) SOIC S08 8-lead (150-Mil) SOIC S8
PIN 1 ID
4
1
1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 3. REFERENCE JEDEC MS-012
0.230[5.842] 0.244[6.197]
0.150[3.810] 0.157[3.987]
4. PACKAGE WEIGHT 0.07gms PART # S08.15 STANDARD PKG. SZ08.15 LEAD FREE PKG.
5
8
0.189[4.800] 0.196[4.978]
SEATING PLANE
0.010[0.254] 0.016[0.406]
X 45
0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0~8 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249]
51-85066-*C
0.0138[0.350] 0.0192[0.487]
All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-07227 Rev. *D
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(c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY2412
Document History Page
Document Title: CY2412 MPEG Clock Generator with VCXO Document Number: 38-07227 REV. ** *A *B *C *D ECN NO. 110492 112457 116961 121879 299735 Orig. of Issue Date Change 10/28/01 03/14/02 08/06/02 12/14/02 See ECN SZV CKN CKN RBI RGL Description of Change Change from Spec number: 38-00898 to 38-07227 Added CY2412-2 to data sheet Removed CY2412-2 from the datasheet. Added CY2412-3 to data sheet Power-up requirements added to Operating Conditions Information Added lead-free for CY2412-1 and CY2412-3 devices
Document #: 38-07227 Rev. *D
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